Is quantum capacitance in graphene a potential hurdle for device scaling?

Transistor size is constantly being reduced to improve performance as well as power consumption. For the channel length to be reduced, the corresponding gate dielectric thickness should also be reduced. Unfortunately, graphene devices are more complicated due to an extra capacitance called quantum capacitance (C Q) which limits the effective gate dielectric reduction. In this work, we analyzed the effect of C Q on device-scaling issues by extracting it from scaling of the channel length of devices. In contrast to previous reports for metal-insulator-metal structures, a practical device structure was used in conjunction with direct radio-frequency field-effect transistor measurements to describe the graphene channels. In order to precisely extract device parameters, we reassessed the equivalent circuit, and concluded that the on-state model should in fact be used. By careful consideration of the underlap region, our device modeling was shown to be in good agreement with the experimental data. C Q contributions to equivalent oxide thickness were analyzed in detail for varying impurity concentrations in graphene. Finally, we were able to demonstrate that despite contributions from C Q, grapheme’s high mobility and low-voltage operation allows for graphene channels suitable for next generation transistors.