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28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique
- Source :
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 22:575-584
- Publication Year :
- 2014
- Publisher :
- Institute of Electrical and Electronics Engineers (IEEE), 2014.
-
Abstract
- We propose a new 2T mask read only memory (ROM) with dynamic column source bias control technique, which enables achieving both high-speed operation and low power consumption. It is also possible to overcome the inherent problem of crosstalk between the bitlines. The fabricated 128-kb ROM macro using 28-nm high- k and metal-gate CMOS bulk technology realizes 0.72 ns read access time at the typical 0.85-V supply voltage, which is comparable to that of recent high-speed embedded static random access memories. The measured dynamic power dissipation is reduced by 50% compared to the conventional 2T ROM. The standby leakage can also be reduced to half that of conventional macros.
- Subjects :
- Imagination
Read-only memory
Hardware_MEMORYSTRUCTURES
Computer science
media_common.quotation_subject
CMOS
Hardware and Architecture
Hardware_INTEGRATEDCIRCUITS
Electronic engineering
Electrical and Electronic Engineering
Macro
Software
Random access
Access time
Voltage
media_common
Leakage (electronics)
Subjects
Details
- ISSN :
- 15579999 and 10638210
- Volume :
- 22
- Database :
- OpenAIRE
- Journal :
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Accession number :
- edsair.doi...........638d91a3ac44e7c00b3e179f38a20ecf