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A CMOS macro array
- Source :
- 1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
- Publication Year :
- 2005
- Publisher :
- Institute of Electrical and Electronics Engineers, 2005.
-
Abstract
- A 1.6μm, 2-level netal, N-well logic array, containing gate array and PLA cells will be reported. The performance and area for a 16b ALU and 16b up-down counter will be compared with a conventional gate array implementation.
- Subjects :
- Diode–transistor logic
AND-OR-Invert
Pass transistor logic
Computer science
Programmable logic array
PMOS logic
Gate array
Electronic engineering
Hardware_ARITHMETICANDLOGICSTRUCTURES
Simple programmable logic device
NMOS logic
Logic optimization
Digital electronics
business.industry
Logic family
Macrocell array
Logic level
Resistor–transistor logic
Programmable logic device
Programmable Array Logic
Integrated injection logic
Logic synthesis
CMOS
Logic gate
business
Computer hardware
Hardware_LOGICDESIGN
Subjects
Details
- Database :
- OpenAIRE
- Journal :
- 1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
- Accession number :
- edsair.doi...........63eebfe1aafe90508e82b8e9f7a28d8b
- Full Text :
- https://doi.org/10.1109/isscc.1986.1156974