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On the Efficiency of Voltage Overscaling under Temperature and Aging Effects
- Source :
- IEEE Transactions on Computers. 68:1647-1662
- Publication Year :
- 2019
- Publisher :
- Institute of Electrical and Electronics Engineers (IEEE), 2019.
-
Abstract
- Voltage overscaling has received extensive attention in the last decade as an attractive paradigm for systems in which resulting timing errors and thus a loss in accuracy can be accepted in exchange for an increase in energy efficiency. At the same time, the delay of a circuit is, in turn, and in addition to voltage, also subject to temperature and aging. Existing work has largely studied voltage overscaling in isolation. This ignores interdependencies with temperature and aging, which can lead to wrong or misleading conclusions. In this work, we are the first to model the combined impact of voltage, temperature and aging on the delay of circuits towards investigating the actual existing trade-offs between efficiency and accuracy provided by voltage overscaling. We show that analyzing voltage in isolation overestimates timing errors and thus underestimates the voltage scaling potential. We further develop an approach that leverages interdependencies to optimize energy, delay and accuracy trade-offs. We precisely translate the individual and combined impact of voltage-, temperature-, and aging-induced delay increase into corresponding probability of error ($P_{error}$Perror). This reveals that the same amount of timing increase results in different error probabilities depending on the origin (i.e., voltage, temperature or aging). For the same timing increase, voltage reductions result in the smallest $P_{error}$Perror compared to temperature or aging, while also reducing temperature- and aging-induced delay increases themselves. This allows voltage reduction to be employed as an effective means to minimize delay, reduce energy and thus maximize efficiency under a given upper bound on error probability. We apply our approach to multipliers in GPUs exploring the trade-off between efficiency and accuracy. We demonstrate how only accounting for voltage scaling alone leads to a considerably larger $P_{error}$Perror (74% on average) than in reality. Our investigation also shows that for the same $P_{error}$Perror constraint, optimizing for combined voltage, temperature and aging effects results, on average, in 116% better energy-delay product (EDP) compared to state of the art.
- Subjects :
- Work (thermodynamics)
Voltage reduction
Hardware_PERFORMANCEANDRELIABILITY
02 engineering and technology
Upper and lower bounds
020202 computer hardware & architecture
Theoretical Computer Science
Computational Theory and Mathematics
Hardware and Architecture
Control theory
Hardware_INTEGRATEDCIRCUITS
0202 electrical engineering, electronic engineering, information engineering
Scaling
Software
Energy (signal processing)
Electronic circuit
Efficient energy use
Voltage
Mathematics
Subjects
Details
- ISSN :
- 23263814 and 00189340
- Volume :
- 68
- Database :
- OpenAIRE
- Journal :
- IEEE Transactions on Computers
- Accession number :
- edsair.doi...........654b2403aae799b3d33fbeae2370fcd1
- Full Text :
- https://doi.org/10.1109/tc.2019.2916869