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A 32 Gb/s Low Power Little Area Re-timer with PI Based CDR in 65 nm CMOS Technology
- Source :
- Communications in Computer and Information Science ISBN: 9789811581342
- Publication Year :
- 2020
- Publisher :
- Springer Singapore, 2020.
-
Abstract
- This paper presents a 32 Gb/s low power little area re-timer with Phase Interpolator (PI) based Clock and Data Recovery (CDR). To further ensure signal integrity, both a Continuous Time Linear Equalizer (CTLE) and Feed Forward Equalizer (FFE) are adapted. To save power dissipation, a quarter-rate based 3-tap FFE is proposed. To reduce the chip area, a Band-Band Phase Discriminator (BBPD) based PI CDR is employed. In addition, a 2-order digital filter is adopted to improve the jitter performance in the CDR loop. This re-timer is achieved in 65 nm CMOS technology and supplied with 1.1 V. The simulation results show that the proposed re-timer can work at 32 Gb/s and consumes 91 mW. And it can equalize >−12 dB channel attenuation, tolerate the frequency difference of 200 ppm.
- Subjects :
- Discriminator
Computer science
020208 electrical & electronic engineering
02 engineering and technology
Chip
01 natural sciences
Power (physics)
010309 optics
CMOS
0103 physical sciences
0202 electrical engineering, electronic engineering, information engineering
Electronic engineering
Signal integrity
Timer
Digital filter
Jitter
Subjects
Details
- Database :
- OpenAIRE
- Journal :
- Communications in Computer and Information Science ISBN: 9789811581342
- Accession number :
- edsair.doi...........69efab183065eee9c25c4e3cc877a053