Multi-core DSP-based implementation of variable data rate OQPSK/TDMA satellite receiver

This paper demonstrates a multi-core DSP-based implementation of variable data rate OQPSK/time division multiple access (TDMA) satellite receiver in the presence of timing, frequency and phase offsets, and with additive white Gaussian noise (AWGN). The implemented receiver uses a 64-bit short preamble for synchronization. It operates at a variable symbol rate of 220Ksps to 660Ksps and gives better bit error rate (BER) performance at low energy per bit to noise density ratio (E b /N 0 ). The proposed receiver operates at a carrier frequency offset upto 15% value normalized to symbol rate. Matlab simulations are used for functional verification of the synchronization algorithm and fixed-point C is used for algorithm implementation. The receiver design is prototyped for 12 TDMA channels in Texas Instruments (TI) multi-core C66x DSPs. The design and implementation of this receiver have been done for C-DOT indigenous satellite project.