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IDDQtest vector selection for transistor short fault testing
- Source :
- Systems and Computers in Japan. 28:11-21
- Publication Year :
- 1997
- Publisher :
- Wiley, 1997.
-
Abstract
- I DDQ testing is indispensable in improving the quality of CMOS circuits. Currently, I DDQ testing is usually conducted by using I DDQ test vectors selected from a test set generated for logic testing. Since I DDQ measurement is relatively slow, it is necessary to select a set of I DDQ test vectors which is as small as possible and which can detect as many faults as possible. In this paper, we consider the problem of I DDQ test vector selection based on the transistor short fault model. First, we define fault equivalence for the transistor short-fault model and propose methods for reducing the number of faults that need to be considered by equivalence fault collapsing. Then, we formalize the I DDQ test vector selection problem and propose a new selection method based on fault tables. Furthermore, we show the effectiveness of the proposed method by experimental results.
- Subjects :
- Computer science
Hardware_PERFORMANCEANDRELIABILITY
Fault (power engineering)
Iddq testing
Theoretical Computer Science
Set (abstract data type)
Computational Theory and Mathematics
Hardware and Architecture
Test vector
Test set
Logic gate
Fault model
Equivalence (measure theory)
Algorithm
Information Systems
Subjects
Details
- ISSN :
- 1520684X and 08821666
- Volume :
- 28
- Database :
- OpenAIRE
- Journal :
- Systems and Computers in Japan
- Accession number :
- edsair.doi...........6a292730d3b2213b247b9601699c8051
- Full Text :
- https://doi.org/10.1002/(sici)1520-684x(199705)28:5<11::aid-scj2>3.0.co;2-r