FPGA-based I/Q chirp generator using first quadrant DDS compression for pulse compression radar

This paper describes the design and development of an FPGA-based signal generator that simultaneously generates dual frequencies I/Q chirp for high-resolution Pulse Compression Radar. We are focusing on implementation of Direct Digital Synthesizer (DDS) algorithm for generating Linear FM (LFM) chirp signal using Verilog programming language for FPGA device. In this paper, we propose a new architecture based on a combination of the property of sine-cosine symmetry and property of sine quadrature for realizing quadrature LFM chirp generator. Experimental result of modified DDS architecture using Altera Stratix IV FPGA confirms the advantage of this technique that results in 87.5% memory reduction. The proposed LFM chirp waveform generator has demonstrated its capability to generate 100MHz quadrature LFM chirp bandwidth.