Two-dimensional numerical analysis of the minimum isolation distance for GaAs digital large-scale integration

The minimum device isolation distance (L/sub min/) applicable to GaAs digital large-scale integrated circuits is presented. The leakage current between two n-type layers formed in a semi-insulating (SI) substrate is simulated using a two-dimensional numerical model, and the results are compared with measurements. It is found that the leakage current is restricted by a potential hump formed by residual acceptors in the SI GaAs substrate when an isolating layer loses its compensated SI property. L/sub min/ is defined as the distance at which there is a leakage current of 1 mA for an isolating layer width of 1 cm. The calculated value of L/sub min/ at room temperature is 1.3 mu m with a bias voltage of 2 V and an acceptor concentration of 10/sup 15/ cm/sup -3/. L/sub min/ decreases to 2/3 of this value when the temperature is reduced from 400 to 100 K, to 1/3 when the acceptor concentration is increased by one order, and to 2/3 when the bias voltage is reduced from 5 to 2 V. >