Synthesis of multiple-valued decision diagrams using current-mode CMOS circuits

In this paper, an algorithm for generating modular designs of Ordered Multiple Decision Diagrams (OMDDs) for Current-Mode CMOS Logic (CMCL) implementation is introduced. The OMDD structures for a set of twelve benchmark circuits from the LGSynth93 using radices ranging from r=2 to r=10 are generated and compared in terms of size and speed. It is observed that MODDs with radices r/spl isin/(2, 4, 8) result in the smallest area. They also achieve the smallest normalized (with respect to the AT/sup 2/ measure for r=2) AT/sup 2/, where A is the area and T is the delay.