Peripheral Circuit Optimization with Pre-charge Technique of Spin Transfer Torque MRAM Synapse Array

Emerging device-based crossbar-array can improve energy efficiency and performance in Spiking Neural Network (SNN) that performs numerous addition and multiplication operations. However, for the large size of crossbar array, delay for SL voltage development increases due to large capacitances of bit-line, and area overhead of peripheral circuit increases significantly. In this paper, we propose STT-MRAM architecture for SNN by minimizing area overhead and operation delay with peripheral circuit optimization. When the proposed method is applied, in 512×512 crossbar array, voltage development delay is reduced by 5.75 (ns), making it possible to perform faster inference operation.