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Ageing-Aware Logic Synthesis
- Source :
- Ageing of Integrated Circuits ISBN: 9783030237806
- Publication Year :
- 2019
- Publisher :
- Springer International Publishing, 2019.
-
Abstract
- CMOS wear-out mechanisms, especially bias temperature instability (BTI), cause growing concerns about circuit reliability. For a logic circuit, the BTI effect increases signal delays, eventually leading to timing violations. Due to the increased demand for circuit density, logic synthesis is currently a significant EDA process to design a circuit with many millions of transistors. Traditional synthesis process does not specifically consider the ageing effects. To ensure reliable operations during the expected lifetime of a circuit, it is necessary to incorporate BTI analysis and optimizations into logic synthesis. This chapter presents case studies about how state-of-the-art techniques can be used to enhance BTI lifetime reliability during synthesis and discusses the advantages and drawbacks of each type of methods.
Details
- ISBN :
- 978-3-030-23780-6
- ISBNs :
- 9783030237806
- Database :
- OpenAIRE
- Journal :
- Ageing of Integrated Circuits ISBN: 9783030237806
- Accession number :
- edsair.doi...........7147b2bd52ad0509af43cd3c554c627b
- Full Text :
- https://doi.org/10.1007/978-3-030-23781-3_5