Reliability in Stacked Gate-All-Around Si Nanowire Devices: Time-Dependent Variability and Full Degradation Mapping

While it is proven that horizontal cylindrical Gate-All-Around (GAA) transistors can enable ultimate MOSFET scaling without the need of disruptive technology changes, the reliability aspects of such devices are still barely characterized and understood. In this work, we will describe the main reliability concerns of these novel devices, comparing their BTI performance with standard FinFETs. Moreover, instead of focusing only on specific reliability issues (e.g. BTI, hot-carrier, TDDB, etc) that are often treated separately, we also assess the degradation of stacked GAA nanowire nFETs in the full {V g , V d } bias space, which allows to identify all the degradation modes and how they interact with each other. The empirical modelling of the degradation includes various channel hot-carrier (CHC) modes as well as BTI and allows an extrapolation to 10-years lifetime in the full bias space.