A Dual-Core Multi-Threaded Xeon Processor with 16MB L3 Cache

Authors :: Stefan Rusu
Harry Muljono
J. Chang
David J. Ayers
Simon M. Tam
Source :: ISSCC
Publication Year :: 2006
Publisher :: IEEE, 2006.
Abstract: A dual-core 64b Xeonreg MP processor is implemented in a 65nm 8M process. The 435mm2 die has 1.328B transistors. Each core has two threads and a unified 1MB L2 cache. The 16MB unified, 16-way set-associative L3 cache implements both sleep and shut-off leakage reduction modes

Subjects :: Smart Cache
Hardware_MEMORYSTRUCTURES
Xeon
CPU cache
Computer science
business.industry
Embedded system
Pipeline burst cache
Page cache
Parallel computing
business
Dual core

Database :: OpenAIRE
Journal :: 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers
Accession number :: edsair.doi...........721538b5ecbb5dfff8e0606dba15defd

Tools