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Length-Matching-Constrained Region Routing in Rapid Single-Flux-Quantum Circuits
- Source :
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 40:945-956
- Publication Year :
- 2021
- Publisher :
- Institute of Electrical and Electronics Engineers (IEEE), 2021.
-
Abstract
- It is known that the pipelined architecture in a rapid single-flux-quantum (RSFQ) circuit can be constructed by inserting a set of path-balancing $D$ -type flip-flops (DFFs) into some gate columns. Based on the assignment of the gates involving the splitters (SPLs) inside each gate column in the placement stage, the passive transmission line (PTL) region between two adjacent gate columns can be formed for a set of 2-pin connections in the routing stage. In this article, given a set of 2-pin connections with length-matching constraints inside one PTL region, based on the efficient utilization of available space in two routing layers, a new grid-based Manhattan routing model can be defined to use available space inside two routing layers for the insertion of the extension lengths on the given connections. To minimize the routing width inside one PTL region, a two-way track-assignment-based routing algorithm using the defined routing model can be first proposed to assign two partitioned sets of vertical intervals onto the used tracks inside two routing layers and connect the corresponding horizontal segments for the given connections with no extension length. Based on the definition of the available areas in the initial two-layer routing result, an iterative flow-based insertion algorithm can be further proposed to insert the feasible detouring paths onto the available areas for the extension lengths on the given connections. If there is no available area for the extension lengths on the unsatisfied connections, an efficient insertion algorithm can be proposed to insert the detouring paths onto one extra area for the extension lengths on the unsatisfied connections. Compared with Kito’s routing algorithm and Cheng’s routing algorithm in length-matching-constrained region routing, the experimental results show that our proposed routing algorithm can use reasonable CPU time to decrease 22.2% and 16.3% of the region width for 12 tested examples on the average, respectively.
- Subjects :
- Matching (graph theory)
Computer science
CPU time
02 engineering and technology
Topology
Grid
Computer Graphics and Computer-Aided Design
020202 computer hardware & architecture
Transmission line
Rapid single flux quantum
Logic gate
Hardware_INTEGRATEDCIRCUITS
0202 electrical engineering, electronic engineering, information engineering
Electrical and Electronic Engineering
Routing (electronic design automation)
Software
Electronic circuit
Subjects
Details
- ISSN :
- 19374151 and 02780070
- Volume :
- 40
- Database :
- OpenAIRE
- Journal :
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Accession number :
- edsair.doi...........730488bbfdc6c1c6e98dff2710730e38
- Full Text :
- https://doi.org/10.1109/tcad.2020.3013576