Low-power area efficient reconfigurable multiplier architecture for FIR filter

Finite Impulse Response (FIR) filters are broadly utilized in many high speed DSP applications. Among the FIR filters reconfigurable FIR filters are having applications in Software Defined Radio and Cognitive Radio. This paper proposes effective consistent multiplier (CM) engineering in light of vertical even parallel regular sub expression disposal calculation for planning a reconfigurable FIR filter. In FIR filter, the product function is computed between the input and constants coefficients defined as the multiple constant multiplication (MCM). This multiplication procedure is connected on to the common reconfigurable FIR channel as the application improvement. Due to the proposed sub expression elimination, the number of addition stage in the multiplication process and the repeated additions were reduced. The proposed multiplier with FIR filter has been designed using verilog coding and implemented in cyclone IV FPGA. The proposed design uses 83% reduced logic utilization and 2% reduces power consumption compared to the FIR filter with normal multiplier. The performance of the proposed design show that the efficiency of the design.