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Dual priority congestion aware shared-resource Network-on-Chip architecture
- Source :
- IEICE Electronics Express. 13:20160142-20160142
- Publication Year :
- 2016
- Publisher :
- Institute of Electronics, Information and Communications Engineers (IEICE), 2016.
- Subjects :
- 010302 applied physics
Network on chip architecture
business.industry
Computer science
Real-time computing
02 engineering and technology
Adaptive routing
DUAL (cognitive architecture)
Condensed Matter Physics
01 natural sciences
020202 computer hardware & architecture
Electronic, Optical and Magnetic Materials
Shared resource
Network congestion
Network on a chip
Slow-start
0103 physical sciences
0202 electrical engineering, electronic engineering, information engineering
Electrical and Electronic Engineering
business
Computer network
Subjects
Details
- ISSN :
- 13492543
- Volume :
- 13
- Database :
- OpenAIRE
- Journal :
- IEICE Electronics Express
- Accession number :
- edsair.doi...........73e5c4dc23c2cf9c8f255c382a976339