RETUNES: Reliable and Energy-Efficient Network-on-Chip Architecture

As the number of cores integrated on the chip increases, the design of reliable and energy-efficient Network-on-Chip (NoC) to support the data movement needed by the multicores is becoming a critical challenge. Reliability of NoC is affected by several aging effects such as Hot carrier injection (HCI) and Negative Bias Temperature Instability (NBTI) which vary the threshold voltage of the transistor, causing timing errors. Dynamic Frequency and Voltage Scaling (DVFS) along with Near Threshold Voltage (NTV) scaling allows the transistor to operate close to the threshold voltage, thereby aggressively minimizing dynamic power consumption by reducing voltage/frequency and minimizing the threshold voltage variation mitigating aging process. However, the trade-off is increased latency and reduced reliability due to lower voltage margins. In this paper, we propose a unified approach called RETUNES: Reliable and Energy-Efficient NoC where NTV scaling and reliability are both achieved while improving performance. RETUNES is a five-level voltage/frequency scaling scheme, which decreases power consumption and threshold voltage variation (?Vth) during low network load with higher reliability and increases the network performance during high network load with reduced reliability. In order to even out the wear out and minimize the impact of aging in NoC, we propose an adaptive routing algorithm in our design. RETUNES improves, total power savings by nearly 2.5x and the energy-delay product (EDP) of the NoC by 3x for Splash-2 and PARSEC benchmarks on a 4 x 4 concentrated mesh architecture.