Cite
A 1.3–4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line
MLA
Gyu Tae Park, et al. “A 1.3–4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line.” IEEE Journal of Solid-State Circuits, vol. 56, June 2021, pp. 1886–96. EBSCOhost, https://doi.org/10.1109/jssc.2020.3045168.
APA
Gyu Tae Park, Jonghyuck Choi, Jincheol Sim, Seungwoo Park, Hyungsoo Kim, Jinil Chung, Hae-Kang Jung, Chulwoo Kim, Yoonjae Choi, Hyunsu Park, Junhyun Chun, Kyeong-Min Kim, & Youngwook Kwon. (2021). A 1.3–4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line. IEEE Journal of Solid-State Circuits, 56, 1886–1896. https://doi.org/10.1109/jssc.2020.3045168
Chicago
Gyu Tae Park, Jonghyuck Choi, Jincheol Sim, Seungwoo Park, Hyungsoo Kim, Jinil Chung, Hae-Kang Jung, et al. 2021. “A 1.3–4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line.” IEEE Journal of Solid-State Circuits 56 (June): 1886–96. doi:10.1109/jssc.2020.3045168.