Deep dive into DDR3 interface jitter contributors

This paper presents a case study of DDR3 interface timing jitter of a DDR subsystem on an evaluation module. The total jitter was separated into various Signal Integrity (SI) and Power Integrity (PI) effects, including signal crosstalk, impedance discontinuities, simultaneous switching noise (SSN), and inter-symbol interference (ISI). Good correlation was achieved between the simulation environment and silicon measurements. The paper also discusses how the study helped guide the package selection for a family of SoC designs.