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A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking
- Source :
- IEEE Journal of Solid-State Circuits. 54:197-209
- Publication Year :
- 2019
- Publisher :
- Institute of Electrical and Electronics Engineers (IEEE), 2019.
-
Abstract
- The graphic DRAM standard GDDR6 is developed to overcome the limitation of previous standards GDDR5/5X for achieving high-speed operation. This paper introduces 16-Gb GDDR6 DRAM with a per-bit trainable single-ended decision feedback equalizer (DFE), a reference impedance (ZQ)-coded transmitter, and a phase-locked loop (PLL)-less clocking to overcome I/O speed limitation by the DRAM process. Furthermore, this paper optimizes clock- and power-domain crossings and adopts split-die architecture to improve signal integrity (SI). This GDDR6 operates 16 Gb/s/pin with 1.15 V and achieves 18 Gb/s/pin with 1.35 V in the DRAM process.
- Subjects :
- Random access memory
business.industry
Computer science
020208 electrical & electronic engineering
Bandwidth (signal processing)
02 engineering and technology
Phase-locked loop
0202 electrical engineering, electronic engineering, information engineering
Signal integrity
Electrical and Electronic Engineering
business
Electrical impedance
Computer hardware
Dram
Subjects
Details
- ISSN :
- 1558173X and 00189200
- Volume :
- 54
- Database :
- OpenAIRE
- Journal :
- IEEE Journal of Solid-State Circuits
- Accession number :
- edsair.doi...........7d08bc4f852cc052f17c7e89b51e1192