A 65 mW 128K EB-ROM

A low power read-only memory (128K EB-ROM) has been developed using direct electron-beam data writing and 2 /spl mu/m VLSI fabrication technology. Programming of information in the ROM is accomplished by selective use of a field oxide in place of a thin gate oxide. The memory cell array is divided into eight current discharge (CD) units. Only one of the eight CD units, which contains a selected cell, is activated by the 3-bit extra decoder. The large capacitance enlarged by the Miller effect is markedly reduced. Moreover, the total capacitance to be precharged is also reduced. High performance output buffer circuitry is adopted, which has a high logic threshold voltage. As a result, the fabricated 128K EB-ROM is capable of 65 mW power dissipation under 400 ns cycle time and 5 V DC supply voltage conditions and 200 ns access time. Memory cell and chip dimensions are 8 /spl mu/m/spl times/7.75/spl mu/m and 3.75 mm/spl times/5.5 mm, respectively.