A bit error and cell loss compensation method for atm transport systems

A bit error correction and cell loss recovery method is proposed to provide high-quality virtual paths in an asynchronous transfer mode (ATM) transport system. This method arranges the cells into a two-dimensional array and performs error correction coding along both dimensions of the array. The error correction code applied in the horizontal direction corrects bit errors and detects lost cell positions. The error correction code applied in the vertical direction restores lost cells. This compensation method requires no processing at the intermediate nodes of the transport system but can be performed after reception of the coded array at the virtual path terminating nodes. Performance estimates are given for this compensation method. It is shown that when a BCH code is used for the horizontal code and a (15, 14) parity code is used for the vertical code on one-tenth of the virtual paths, then improvements of approximately seven and ten orders of magnitude are achieved in cell loss and bit error rates, respectively. In this case, the communication efficiency is reduced by 10 percent on those paths that employ error correction coding.