Experimental Study of Physical-Vapor-Deposited Titanium Nitride Gate with An n+-Polycrystalline Silicon Capping Layer and Its Application to 20 nm Fin-Type Double-Gate Metal–Oxide–Semiconductor Field-Effect Transistors

We have comparatively investigated the electrical characteristics including threshold voltage (V th) variability and mobility by fabricating n+-polycrystalline silicon (poly-Si) gate and physical-vapor-deposited (PVD) titanium nitride (TiN) gate fin-type double-gate metal–oxide–semiconductor field-effect transistors (FinFETs), and demonstrated 20-nm-thick PVD-TiN gate FinFETs with a symmetrical V th. It is experimentally found that the gate stack of a 20-nm-thick PVD-TiN layer capped with a 100-nm-thick n+-poly-Si layer is very effective for setting a symmetrical V th for undoped FinFETs keeping almost the same V th variability and mobility as those in the case of the n+-poly-Si gate only. On the other hand, mobility degradation was observed in the case of pure 50-nm-thick PVD-TiN gates. These results indicate that mobility degradation probably caused by the thick metal gate induced mechanical stress can be effectively suppressed by reducing the PVD-TiN thickness to 20 nm or less.