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EIGER: Next generation single photon counting detector for X-ray applications

Authors :
Aldo Mozzanica
E. Schmid
B. Henrich
Ian Johnson
Bernd Schmitt
Roberto Dinapoli
Akos Schreiber
Xintian Shi
Anna Bergamaschi
Gerd Theidel
Roland Horisberger
Source :
Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment. 650:79-83
Publication Year :
2011
Publisher :
Elsevier BV, 2011.

Abstract

EIGER is an advanced family of single photon counting hybrid pixel detectors, primarily aimed at diffraction experiments at synchrotrons. Optimization of maximal functionality and minimal pixel size (using a 0.25 μ m process and conserving the radiation tolerant design) has resulted in 75 × 75 μ m 2 pixels. Every pixel comprises a preamplifier, shaper, discriminator (with a 6 bit DAC for threshold trimming), a configurable 4/8/12 bit counter with double buffering, as well as readout, control and test circuitry. A novel feature of this chip is its double buffered counter, meaning a next frame can be acquired while the previous one is being readout. An array of 256×256 pixels fits on a ∼ 2 × 2 cm 2 chip and a sensor of ∼ 8 × 4 cm 2 will be equipped with eight readout chips to form a module containing 0.5 Mpixel. Several modules can then be tiled to form larger area detectors. Detectors up to 4×8 modules (16 Mpixel) are planned. To achieve frame rates of up to 24 kHz the readout architecture is highly parallel, and the chip readout happens in parallel on 32 readout lines with a 100 MHz Double Data Rate clock. Several chips and singles (i.e. a single chip bump-bonded to a single chip silicon sensor) were tested both with a lab X-ray source and at Swiss Light Source (SLS) beamlines. These tests demonstrate the full functionality of the chip and provide a first assessment of its performance. High resolution X-ray images and “high speed movies” were produced, even without threshold trimming, at the target system frame rates (up to ∼ 24 kHz in 4 bit mode). In parallel, dedicated hardware, firmware and software had to be developed to comply with the enormous data rate the chip is capable of delivering. Details of the chip design and tests will be given, as well as highlights of both test and final readout systems.

Details

ISSN :
01689002
Volume :
650
Database :
OpenAIRE
Journal :
Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment
Accession number :
edsair.doi...........88a5d37968acc5698292d1041d89472b
Full Text :
https://doi.org/10.1016/j.nima.2010.12.005