FPGA Implementation of AES Encryption Optimization Algorithm

To improve the confidentiality of data transmission and the efficiency of encryption and decryption, this paper uses FPGA to improve the traditional AES encryption algorithm. The scheme uses pipeline technology to optimize the structure of AES algorithm, including the key expansion part and the encryption and decryption part. Then, the AES encryption algorithm in 128bit initial key mode is implemented, and the bit width conversion module is written, so that the encryption part can be connected with other types of bus. The experimental analysis uses Quartus tool to compile AES algorithm, and establish entity PCB circuit to test in real environment. The experimental results show that the optimization algorithm can complete the encryption and decryption function, and improve the data throughput and clock frequency.