A fast method for timing verification that uses the conditions that cause changes in the output values of gates

Subjects :: Sequential logic
Computational Theory and Mathematics
Computer engineering
Hardware and Architecture
Computer science
Circuit design
Algorithm
Information Systems
Theoretical Computer Science

ISSN :: 1520684X and 08821666
Volume :: 32
Database :: OpenAIRE
Journal :: Systems and Computers in Japan
Accession number :: edsair.doi...........8c7c318453245d567c437fcf0ab3b628
Full Text :: https://doi.org/10.1002/1520-684x(200101)32:1<38::aid-scj5>3.0.co;2-f

Full Text Access

Tools