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Microarchitectural dl/dt control

Authors :
David J. Ayers
E. Grochowski
Vivek Tiwari
Source :
IEEE Design & Test of Computers. 20:40-47
Publication Year :
2003
Publisher :
Institute of Electrical and Electronics Engineers (IEEE), 2003.

Abstract

This article takes a high level of the power-grid noise problem as it relates to the microarchitectural definition of an IC. Through a set of simulations, the authors relate the noise problem to the details of the circuit and clocking implementation giving insight into the possible method to reduce such noise.

Details

ISSN :
07407475
Volume :
20
Database :
OpenAIRE
Journal :
IEEE Design & Test of Computers
Accession number :
edsair.doi...........90ba66a1a19e22572017f20d89c1a160
Full Text :
https://doi.org/10.1109/mdt.2003.1198684