Valid test pattern identification for VLSI adaptive test

With continuously decreasing circuit scale, more and more test patterns (test contents) are added to test set to achieve acceptable defect levels, which seriously affect test time and, consequently, test cost. Theoretically, dropping invalid (pattern that can make the test pass) test patterns can reduce test cost. In fact, When the valid (pattern that can make the test fail) and invalid patterns overlap seriously, identifying effective patterns performs poorly, which will not achieve the expected results. This paper proposes a kind of eliminate redundancy method, so that this LDA-MRMR algorithm which can provide test cost reduction without increasing the defect level obviously. Experimental results demonstrate that the proposed method sacrifices 3% of the predictive accuracy in exchange for 3.7 times time saving compared with traditional methods. In addition, the algorithm is completely software-based and does not require any additional hardware overhead and is directly compatible with traditional integrated circuit testing process.