Optimized Hardware Implementation of Enhanced TRIPLE-DES using Cluster LUT and Pipelining on SPARTEN FPGA

MLA

Noha Hussen, et al. “Optimized Hardware Implementation of Enhanced TRIPLE-DES Using Cluster LUT and Pipelining on SPARTEN FPGA.” International Journal of Computer Applications, vol. 164, Apr. 2017, pp. 5–14. EBSCOhost, https://doi.org/10.5120/ijca2017913608.

APA

Noha Hussen, Amany Sarhan, & Marwa Fayez. (2017). Optimized Hardware Implementation of Enhanced TRIPLE-DES using Cluster LUT and Pipelining on SPARTEN FPGA. International Journal of Computer Applications, 164, 5–14. https://doi.org/10.5120/ijca2017913608

Chicago

Noha Hussen, Amany Sarhan, and Marwa Fayez. 2017. “Optimized Hardware Implementation of Enhanced TRIPLE-DES Using Cluster LUT and Pipelining on SPARTEN FPGA.” International Journal of Computer Applications 164 (April): 5–14. doi:10.5120/ijca2017913608.