A Digital Root Based Modular Reduction Technique for Power Efficient, Fault Tolerance in FPGAs

Recent advancements in performance, logic density, and power consumption of Field-Programmable Gate Arrays (FPGAs) have made them attractive for their widespread adoption into automotive, aircraft, space, military, and other safety-critical applications, in both embedded systems and cloud computing platforms. Every year, though, it becomes harder and harder to benefit from such advances in technology scaling due to smaller voltage margins, more aggressive clocking schemes, and greater device variability. FPGAs are often expected to last years or even decades in a variety of different environments before replacement. In some applications, they can be susceptible to soft and transient errors due to Single Event Upsets (SEUs), environment, and aging related effects. In this paper, we propose a simplified modular arithmetic technique based upon the concept of the digital root (DR) to monitor soft and transient errors, with low area overhead and high rates of detectability. The technique can be easily implemented at the register-transfer level (RTL) with no need to modify the underlying hardware of the FPGA. In one experiment, after dropping the supply voltage well below recommended design margins, we show in situ measurements on the instantaneous error rate in an Intel Arria 10 GX FPGA, which can be leveraged to optimize the power-performance trade-off of already deployed designs. We demonstrate this tradeoff, using an inherently error tolerant low-density parity-check (LDPC) decoder block, by either increasing the system clock beyond its synthesized target to achieve a 50% improvement in throughput, or by lowering the FPGA's supply voltage below synthesized design margins for a 65% reduction in power.