Back to Search
Start Over
Vertical-Gate Si/SiGe Double-HBT-Based Capacitorless 1T DRAM Cell for Extended Retention Time at Low Latch Voltage
- Source :
- IEEE Electron Device Letters. 33:134-136
- Publication Year :
- 2012
- Publisher :
- Institute of Electrical and Electronics Engineers (IEEE), 2012.
-
Abstract
- A vertical-gate Si/SiGe double heterojunction bipolar transistor (VerDHBT)-based capacitorless 1T DRAM cell is proposed for improved storage performance with a fabrication feasibility through a selective epitaxy. It is verified through a TCAD device simulation for dc and transient characteristics of the proposed VerDHBT-based 1T DRAM. The off-state leakage current was significantly reduced, while the on-current was considerably increased with SIF/Bmid/DIF = SiGe/SiGe/Si as the interfacial source/middle body/interfacial drain. A large hysteresis window for the “read 1” from the “read 0” and a long retention time at low latch voltage could be also obtained.
- Subjects :
- Fabrication
Materials science
business.industry
Heterojunction bipolar transistor
Electrical engineering
Hardware_PERFORMANCEANDRELIABILITY
Electronic, Optical and Magnetic Materials
Silicon-germanium
chemistry.chemical_compound
Hysteresis
chemistry
Logic gate
Hardware_INTEGRATEDCIRCUITS
Optoelectronics
Transient (oscillation)
Electrical and Electronic Engineering
business
Dram
Voltage
Subjects
Details
- ISSN :
- 15580563 and 07413106
- Volume :
- 33
- Database :
- OpenAIRE
- Journal :
- IEEE Electron Device Letters
- Accession number :
- edsair.doi...........94ac564c1a286c5392798d0cace9fa5e