Cite

Thru silicon via stacking & numerical characterization for multi-die interconnections using full array & very fine pitch micro C4 bumps

MLA

C. Surasit, et al. “Thru Silicon via Stacking & Numerical Characterization for Multi-Die Interconnections Using Full Array & Very Fine Pitch Micro C4 Bumps.” 2011 IEEE 61st Electronic Components and Technology Conference (ECTC), May 2011. EBSCOhost, https://doi.org/10.1109/ectc.2011.5898529.



APA

C. Surasit, John D. Beleran, K. Y. Au, C. H. Toh, Y.B. Yang, Y. F. Zhang, Y. S. Koh Drake, P. L Ong Wilson, & S. L. Kriangsak. (2011). Thru silicon via stacking & numerical characterization for multi-die interconnections using full array & very fine pitch micro C4 bumps. 2011 IEEE 61st Electronic Components and Technology Conference (ECTC). https://doi.org/10.1109/ectc.2011.5898529



Chicago

C. Surasit, John D. Beleran, K. Y. Au, C. H. Toh, Y.B. Yang, Y. F. Zhang, Y. S. Koh Drake, P. L Ong Wilson, and S. L. Kriangsak. 2011. “Thru Silicon via Stacking & Numerical Characterization for Multi-Die Interconnections Using Full Array & Very Fine Pitch Micro C4 Bumps.” 2011 IEEE 61st Electronic Components and Technology Conference (ECTC), May. doi:10.1109/ectc.2011.5898529.