Back to Search
Start Over
A self-aligned gate superlattice (Al,GA)As/n+-GaAs MODFET 5 × 5-bit parallel multiplier
- Source :
- IEEE Electron Device Letters. 7:700-702
- Publication Year :
- 1986
- Publisher :
- Institute of Electrical and Electronics Engineers (IEEE), 1986.
-
Abstract
- A 5 × 5-bit parallel multiplier circuit has been demonstrated with self-aligned gate superlattice (Al,Ga)As/n+-GaAs modulation-doped FET's (MODFET's). Multiplication times (gate delays) and corresponding power dissipations of 1.80 ns (73 ps/gate) at 0.43 mW/gate and 1.08 ns (43 ps/gate) at 0.75 mW/gate were measured at room temperature and 77 K, respectively. These are the shortest gate propagation delays ever reported for parallel multiplier circuits at room temperature or 77 K using any semiconductor IC technology.
- Subjects :
- Adder
Materials science
business.industry
Electrical engineering
Integrated circuit
Self-aligned gate
Analog multiplier
Electronic, Optical and Magnetic Materials
law.invention
Gallium arsenide
chemistry.chemical_compound
chemistry
law
Logic gate
Optoelectronics
Field-effect transistor
Electrical and Electronic Engineering
business
Electronic circuit
Subjects
Details
- ISSN :
- 07413106
- Volume :
- 7
- Database :
- OpenAIRE
- Journal :
- IEEE Electron Device Letters
- Accession number :
- edsair.doi...........9ae44ed3b91c9ab2a45a789d70d2ef73