Aging-Aware Gate-Level Modeling for Circuit Reliability Analysis

MLA

Ru Huang, et al. “Aging-Aware Gate-Level Modeling for Circuit Reliability Analysis.” IEEE Transactions on Electron Devices, vol. 68, Sept. 2021, pp. 4201–07. EBSCOhost, https://doi.org/10.1109/ted.2021.3096171.

APA

Ru Huang, Zuodong Zhang, Zhe Zhang, Joddy Wang, Dehuang Wu, Xuguang Shen, Runsheng Wang, & Jiayang Zhang. (2021). Aging-Aware Gate-Level Modeling for Circuit Reliability Analysis. IEEE Transactions on Electron Devices, 68, 4201–4207. https://doi.org/10.1109/ted.2021.3096171

Chicago

Ru Huang, Zuodong Zhang, Zhe Zhang, Joddy Wang, Dehuang Wu, Xuguang Shen, Runsheng Wang, and Jiayang Zhang. 2021. “Aging-Aware Gate-Level Modeling for Circuit Reliability Analysis.” IEEE Transactions on Electron Devices 68 (September): 4201–7. doi:10.1109/ted.2021.3096171.