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A 10-GHz 8-b multiplexer/demultiplexer chip set for the SONET STS-192 system

Authors :
N. Uchitomi
K. Ishida
Mitsuo Konno
Shoichi Shimizu
Toshihiro Suzuki
Yoshiaki Kitaura
Kenichi Tomita
Hirotsugu Wakimoto
Kunio Yoshihara
Source :
IEEE Journal of Solid-State Circuits. 26:1936-1943
Publication Year :
1991
Publisher :
Institute of Electrical and Electronics Engineers (IEEE), 1991.

Abstract

An ultrahigh-speed 8-b multiplexer (MUX) and demultiplexer (DMUX) chip set has been developed for the synchronous optical network (SONET) next-generation optical-fiber communication systems, which will require data bit rates of about 10 Gb/s. These ICs were designed using three novel concepts: a tree-type architecture giving reliable operation, a dynamic divider with a wide operating range, and a 50- Omega on-chip transmission line with high-speed pulse propagation. They were fabricated using a 0.5- mu m WN/sub x/-gate GaAs MESFET process. The DMUX and MUX operated at up to 10.4 and 11.4 GHz, respectively, both with an adequate phase margin of more than 230 degrees . >

Details

ISSN :
00189200
Volume :
26
Database :
OpenAIRE
Journal :
IEEE Journal of Solid-State Circuits
Accession number :
edsair.doi...........a197011480b671334a00da14abddbc77
Full Text :
https://doi.org/10.1109/4.104187