Methodology for thermal budget reduction of SPER down to 450 °C for 3D sequential integration

3D sequential integration enables the full use of the third dimension thanks to its unique contact density far above the possibilities of 3D packaging solutions. However, as the transistors are sequentially stacked over each other, the thermal budget allowed for the fabrication of the top transistor is limited by the maximal temperature accepted by the already made bottom one. It was previously described that a thermal budget of T > 500 °C is enough to degrade the bottom transistors performance. So the technological challenge is to develop low temperature routines for the fabrication of the top devices. For that, different processes have to be adapted, mainly the dopant activation step, where the T > 1000 °C spike annealing must be replaced. In this contribution, we present the feasibility to dope by solid phase epitaxial regrowth (SPER) at 450 °C thin Si films (22 nm) containing high dopant concentration of 5 × 10 20 at/cm 3 . For n- and p-type dopants, the 450 °C SPER rendered low sheet resistance values, as low as the ones obtained with the high temperature activation method.