A Comprehensive Compact Model for GaN HEMTs, Including Quasi-Steady-State and Transient Trap-Charge Effects

A comprehensive scalable trap-charge model for the dc and pulsed $I$ – $V$ modeling of GaN high electron-mobility transistor is presented. While interface traps are considered for dc $I$ – $V$ modeling, surface states and traps in the AlGaN barrier and GaN buffer are considered for the pulsed $I$ – $V$ model. A surface-potential-based model is presented for interface traps, which is then adapted to the current model for the dc modeling. For the pulsed $I$ – $V$ modeling, a semiempirical approach is proposed for gate lag as well as both gate-lag and drain-lag conditions. The model is able to capture the effects of gate ( $V_{\mathrm{ gq}})$ and drain ( $V_{\mathrm{ dq}})$ quiescent biases as well as the stress time ( $T_{\mathrm{\scriptscriptstyle OFF}})$ , and is validated with both numerical simulation and measurement data. Finally, for the accurate transient simulations in switching applications, the emission of electrons is also modeled in Verilog-A using an asymptotic solution of a differential equation, which can be a better alternative to that of the $RC$ subcircuit approach.