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A fault tolerant approach to microprocessor design

Authors :
Todd Austin
Christopher T. Weaver
Source :
DSN
Publication Year :
2002
Publisher :
IEEE Comput. Soc, 2002.

Abstract

We propose a fault-tolerant approach to reliable microprocessor design. Our approach, based on the use of an online checker component in the processor pipeline, provides significant resistance to core processor design errors and operational faults such as supply voltage noise and energetic particle strikes. We show through cycle-accurate simulation and timing analysis of a physical checker design that our approach preserves system performance while keeping area overheads and power demands low. Furthermore, analyses suggest that the checker is a fairly simple state machine that can be formally verified, scaled in performance, and reused. Further simulation analyses show virtually no performance impacts when our simple checker design is coupled with a high-performance microprocessor model. Timing analyses indicate that a fully synthesized unpipelined 4-wide checker component in 0.25 /spl mu/m technology is capable of checking Alpha instructions at 288 MHz. Physical analyses also confirm that costs are quite modest; our prototype checker requires less than 6% the area and 1.5% the power of an Alpha 21264 processor in the same technology. Additional improvements to the checker component are described which allow for improved detection of design, fabrication and operational faults.

Details

Database :
OpenAIRE
Journal :
Proceedings International Conference on Dependable Systems and Networks
Accession number :
edsair.doi...........a63860db350fa60e6ae7113a22953c8f
Full Text :
https://doi.org/10.1109/dsn.2001.941425