Trace line Layout Design of FO-WLCSP

Establishing a stress buffer layer under a solder ball is an effective method to improve the reliability of solder balls. However, large deformation of the stress buffer layer leads to a decrease in trace line reliability. In this study, we discussed the trace line reliability of FO-WLCSP structures after thermal cycling tests. We use three-dimensional finite element methods to analyze trace line reliability and the simulation process has been validated. This study designed and discussed many different wiring patterns. Simulation results show that stress and strain are mainly concentrated in the via, chip/filler interface and pad junction. In addition, the study also discussed the effect of delamination on trace line reliability. The simulation results show that the longer and deeper delamination along the interface boundary of the chip and molding compound, the worse the reliability of the trace line.