On-chip Analysis of Etched Drain based Cyl. GAA TFET with Elevated Density Strip

This paper comprises of, designing and analysis of novel 3D Gate All Around Cylindrical tunnel field effect transistor (TFET). The device designing incorporates hetero-substrate (HeS) material with inclusion of etched drain (ED) and elevated density strip (EDS) at source-to-channel junction for reduction in tunneling barrier width resulting in better ON-current (ION). For analysis purpose of device, investigation is carried out in terms of drain current profile, subthreshold swing (SS) and parasitic capacitances. The device has been recorded with steepest SS=35mV/Dec, robust OFF-current (IOFF)=1.51X10−19 A/µm, high ION=1.52X10−5 A/µm. Designing and analysis of the proffered structure has been executed using Technology Computer-Aided Design (TCAD) 3D device computation software.