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A 10-bit 100 MS/s CMOS current-steering DAC
- Source :
- 2016 IEEE International Conference on Ubiquitous Wireless Broadband (ICUWB).
- Publication Year :
- 2016
- Publisher :
- IEEE, 2016.
-
Abstract
- A 10-bit, 100MS/s digital-to-analog converter (DAC) is designed in a standard 0.18μm CMOS process, where a segmented current-steering technique is employed. Through elaborative comparison among different decoding strategies, a “6+4” segmented architecture is used to obtain a balance between area cost and performance. In order for excellent performance, an array of current sources based on a regulated cascode current mirror technique is used to achieve both high output impedance and large-swing output voltage. A latch with functions of amplitude limiting and clock synchronization is employed to reduce glitches and improve dynamic performance. From a single 1.8 V supply, simulation results show that a full-scale current of 8 mA, a differential non-linear (DNL) of ±0.1LSB, an integral nonlinear error (INL) of ±0.4LSB, and a spurious-free dynamic range (SFDR) of 52dB are achieved.
- Subjects :
- 0209 industrial biotechnology
Engineering
Spurious-free dynamic range
business.industry
Dynamic range
Electrical engineering
02 engineering and technology
Clock synchronization
020901 industrial engineering & automation
CMOS
Integral nonlinearity
Hardware_INTEGRATEDCIRCUITS
Electronic engineering
Output impedance
business
Decoding methods
Voltage
Subjects
Details
- Database :
- OpenAIRE
- Journal :
- 2016 IEEE International Conference on Ubiquitous Wireless Broadband (ICUWB)
- Accession number :
- edsair.doi...........a8acf7ca6726105994ffe3a9c8906115