Development of a VLSI chip for real time MPEG-2 video decoder

A VLSI chip fully compatible with ISO/IEC 13818 2 (MPEG-2 video) has been developed. The chip is conforming to main profile @ main level of the standard, which realizes real-time decoding of ITU-R Rec.601 format moving pictures. In addition, it is also designed to operate as a part of MPEG-2 encoder. The chip size and power dissipation are minimized by optimizing its architecture and by using hardware macro cells for bulky circuits such as multipliers. As a result, the chip has been implemented with approximately 620K transistors on 11.35/spl times/11.35 mm using a triple metal 0.5 /spl mu/m CMOS technology. The chip has performed well in evaluations on a PC-based testbed.