An integrated temporal partitioning and physical design framework for static compilation of reconfigurable computing systems

Lack of appropriate compilers for generating configurations and their scheduling is one of the main challenges in the development of reconfigurable computing systems. In this paper, a new iterative design flow for reconfigurable computing systems is proposed that integrates the synthesis and physical design phases to perform a static compilation process. We propose a new temporal partitioning algorithm for partitioning and scheduling, which attempts to decrease the time of reconfiguration on a partially reconfigurable hardware. In addition, we perform an incremental physical design process based on similar configurations produced in the partitioning stage. To validate the effectiveness of our methodology and algorithms, we developed a framework according to the proposed methodology.