Drain current reduction by source electrode overlap in hydrogenated amorphous silicon thin‐film transistors

The characteristics of hydrogenated amorphous silicon (a‐Si:H) thin‐film transistors are investigated as a function of the overlap of the source electrode Lovs on top of the passivation layer. The drain current is reduced by Lovs and the effect is dependent on drain voltage and a‐Si:H layer thickness. The effect is enhanced at high drain voltage and at thin a‐Si:H layer thickness. At high drain voltage, field‐effect mobility and threshold voltage decrease as Lovs increases. Numerical calculation of carrier concentration in a‐Si:H layer showed that the carrier is depleted under Lovs and that the effective channel length is shortened by the size of Lovs. The nonlinear resistance formed by Lovs is discussed in terms of drain voltage and a‐Si:H layer thickness.