3-D Quasi-Atomistic Model for Line Edge Roughness in Nonplanar MOSFETs

As the physical sizes of devices have been scaled down, the negative impact of process-induced random variation on device performance has increased; therefore, there is an urgent demand for advanced simulation methods for variation. In this paper, a 3-D quasi-atomistic simulation methodology for line edge roughness (LER) in nonplanar devices, such as FinFETs and gate-all-around (GAA) FETs, is proposed. In addition, a simple gate oxide layer model is proposed to analyze the impact of LER on device performance while excluding the impact of oxide thickness variation. To verify the importance of the quasi-atomistic 3-D LER model and to compare the LER-induced performance variation in a FinFET to that in a GAA FET, the case studies using the 3-D quasi-atomistic LER model for FinFETs and GAA FETs are performed.