FDSOI vs FinFET: differentiating device features for ultra low power & IoT applications

This paper reviews the main differentiating features of planar FDSOI devices vs planar bulk and 3D FinFETs for ultra-low power and IoT (Internet of Things) applications. The interest of using back-bias, the specific FDSOI device/design feature, to maximize the performance/power efficiency, to mitigate the process variability and to suppress the leakage is highlighted in this paper. Low parasitic gate capacitance, low V T mismatch associated with its undoped channel, and low gate resistance linked to the gate-first integration also bring some competitive advantages to FDSOI over FinFETs for Analog and RF devices.