Performance evaluation of the memory hierarchy design on CMP prototype using FPGA

The importance of the memory hierarchy has increased with advances in performance of processors in Chip Multi-Processor(CMP) system. However, the research of on chip memory subsystem for Multiprocessor has not been undertaken thoroughly. In this paper, we develop two distributed shared memory hierarchies based on distributed shared-bus and Network-on-Chip(NoC), and the performances of these prototype designs are evaluated under JPEG decoding application, and implement them on a FPGA device. We compare the performance between the different on chip memory subsystem with the application, and the results show that the distributed shared memory hierarchy based on distributed shared-bus provides the best performance of speedup ratio with the least processor and that the NoC memory hierarchy provides the best performance of speedup ratio with the more processors.