Closed-form expression for capacitance of tapered through-silicon-vias considering MOS effect

In this paper, closed-form expression of the parasitic capacitance of the tapered Through-Silicon Via (TSV) is proposed, which also cover the cylindrical TSV when the slop wall angle is 90°. The comparison between the results of Ansoft Q3D verification and Matlab calculation are made. It shows that the root mean square error is less than 6.10%, over a wide range of the bottom radius and the height of tapered TSV, and the oxide thickness, therefore, the expression presented proves to be accurate.