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Reliability issues of offset drain transistors after different modes of static electrical stress
- Source :
- Microelectronics Reliability. 33:1921-1933
- Publication Year :
- 1993
- Publisher :
- Elsevier BV, 1993.
-
Abstract
- The reliability issues of Offset Drain Transistors (ODT's) after different modes of static electrical stress (high voltage uniform gate stress, high voltage drain stress and hot carrier stress) are presented. Besides, the evolution of the macroscopic electrical parameters of these devices after high voltage uniform gate stress, has been attributed quantitatively to the evolution of the bulk gate oxide trapping characteristics and the variation of the Si/SiO 2 interface state charge. Furthermore, qualification of these devices for application in non-volatile memory arrays as bit select transistor has been conducted.
- Subjects :
- Engineering
Offset (computer science)
business.industry
Transistor
Electrical engineering
High voltage
Drain-induced barrier lowering
Hardware_PERFORMANCEANDRELIABILITY
Trapping
Condensed Matter Physics
Hot carrier stress
Atomic and Molecular Physics, and Optics
Surfaces, Coatings and Films
Electronic, Optical and Magnetic Materials
law.invention
Hardware_GENERAL
Gate oxide
law
Hardware_INTEGRATEDCIRCUITS
Optoelectronics
Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality
business
Subjects
Details
- ISSN :
- 00262714
- Volume :
- 33
- Database :
- OpenAIRE
- Journal :
- Microelectronics Reliability
- Accession number :
- edsair.doi...........c1f252178dc0530e73fc86dc8594f4eb